Currently, forwarding performance of a network device may be tested by a test apparatus shown in FIG. 1. The test apparatus shown in FIG. 1 includes a central processing unit (CPU), a traffic emulation apparatus, a to-be-tested network device, and a traffic check apparatus. The traffic emulation apparatus includes: a traffic control module, configured to control a traffic packet transmission parameter (for example, a packet transmission time, a packet transmission quantity, and a packet transmission interval); a static random access memory (SRAM, Static Random Access Memory), configured to store a user packet; and a traffic initiation module, configured to initiate traffic. A basic principle is as follows: The CPU controls the traffic emulation apparatus to send user traffic; the to-be-tested network device forwards, to the traffic check apparatus, the user traffic sent by the traffic emulation apparatus; the traffic check apparatus performs analysis, check, and statistics collection on the user traffic forwarded by the to-be-tested network device, so as to analyze forwarding performance of the to-be-tested network device. It can be learned that the user traffic sent by the traffic emulation apparatus is very important to a test of the forwarding performance of the network device.
In an Ethernet layer-2 test and an Ethernet layer-3 test, the CPU usually controls the traffic emulation apparatus in the test apparatus shown in FIG. 1 to send the user traffic in a generation manner based on field programmable gate array (FPGA,
Field Programmable Gate Array) dedicated hardware. A schematic diagram of a principle is shown in FIG. 2. Before the user traffic is generated, the CPU stores configuration information of a user packet into an on-chip SRAM, stores header information of the user packet into a SRAM (an on-chip SRAM or an off-chip SRAM), and cyclically fetches the header information stored in the SRAM in a user traffic generation phase, so as to generate the user traffic. In the generation manner based on FPGA dedicated hardware, generation of ultrafast broadband traffic and precise control of user traffic can be implemented. However, a quantity of user packets is limited by a size of SRAM space. As a result, in the generation manner based on FPGA dedicated hardware, storage of a mass of user packets cannot be implemented, and the user traffic cannot be generated at a line rate.